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HV257 HV257
Demo Kit Available
32-Channel High Voltage Sample and Hold Amplifier Array
General Description
The Supertex HV257 is a 32-channel high voltage sample and hold amplifier array integrated circuit. It operates on a single high voltage supply, up to 300V, and two low voltage supplies, VDD and VNN. All 32 sample and hold circuits share a common analog input, Vsig. The individual sample and hold circuits are selected by a 5 to 32 logic decoder. The sampled voltage on the holding capacitor is buffered by a low voltage amplifier and amplified by a high voltage amplifier with a closed loop gain of 72V/V. The internal closed loop gain is set for an input voltage range of 0V to 4.096V. The input voltage can be up to 5.0V, but the output will saturate. The maximum output voltage swing is 5V below the VPP high voltage supply. The outputs can drive capacitive loads of up to 3000pF. The maximum output source and sink current can be adjusted by using two external resistors. An external RSOURCE resistor controls the maximum sourcing current and an external RSINK resistor controls the maximum sinking current. The current limit is approximately 12.5V divided by the external resistor value. The setting is common for all 32 outputs. A low voltage silicon junction diode is made available to help monitor the die temperature.
Features
32 independent high voltage amplifiers
300V operating voltage 295V output voltage 2.2V/s typical output slew rate Adjustable output current source limit Adjustable output current sink limit Internal closed loop gain of 72V/V 12M feedback impedance Layout ideal for die applications
Application
MEMS (microelectromechanical systems) driver Piezoelectric transducer driver Optical crosspoint switches (using MEMS technology)
Typical Application
Supertex HV257
DAC VSIG Low Voltage Power Supply
High Voltage Power Supply HVOUT0 HVOUT1 HVOUT2 HVOUT3
x y y x
Micro Processor
A0 A1 A2 A3 A4 EN DGND 32 Low Voltage Channel Select Sample and Hold High Voltage OpAmp Array
MEMS Array HVOUT30 HVOUT31
RSOURCE RSINK
AGND VNN
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HV257
Ordering Information
Device HV257 Maximum Output Voltage 295V Nominal Closed Loop Gain 72V/V Package Options 100Lead MQFP HV257FG Die HV257X
Absolute Maximum Ratings*
VPP, High voltage supply AVDD, Analog low voltage positive supply DVDD, Digital low voltage positive supply AVNN, Analog low voltage negative supply DVNN, Digital low voltage negative supply Logic input voltage VIN, Analog input signal Storage temperature range Maximum junction temperature 310V 8.0V 8.0V -7.0V -7.0V -0.5V to DVDD 0V to 6.0V -65C to 150C 150C
*Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Electrical Characteristics
Symbol Parameters
(Over operating conditions unless otherwise noted.)
Min
Typ
Max
Unit
Condition
Operating Conditions
VPP V DD VNN IPP I DD I NN TJ High voltage positive supply Low voltage positive supply Low voltage negative supply VPP supply current VDD supply current VNN supply current Junction temperature range -5.2 -10 125 125 6.0 -4.5 300 7.5 -6.5 0.8 4.3 V V V mA mA mA C VPP = 300V, All HVOUT = 0V, No Load VDD = 6.0V to 7.5V VNN = -4.5V to -6.5V
High Voltage Amplifier
HVOUT VINOS SR BW AO AV R FB CLOAD ISOURCE ISINK HVOUT voltage swing Input voltage offset HVOUT slew rate rise HVOUT slew rate fall HVOUT -3dB channel bandwidth Open loop gain Closed loop gain Feedback resistance from HVOUT to ground HVOUT capacitive load HVOUT sourcing current limiting range HVOUT sinking current limiting range 70 68.4 9.6 0 385 385 25 25 -80 -40 550 550 2.2 2.0 4.0 100 72.0 12 3000 715 715 250 250 75.6 0 VPP -5 50 V mV V/s V/s KHz dB V/V M pF A A K K dB dB
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Input referred. No Load No Load VPP = 300V
RSOURCE = 25K RSINK = 25K
External resistance range for setting current RSOURCE source limit RSINK CTDC PSRR External resistance range for setting current sink limit DC channel to channel crosstalk
Power supply rejection ratio for VPP, VDD, and VNN
2
HV257
Sample and Hold
Symbol VPED RSW C RDROOP VSIG Pedestal Voltage Sample and Hold Switch resistance Sample and Hold Capacitor Droop rate during hold time relative to input Input voltage range 0 Parameter Min Typ 1.0 5.0 10 12.0 2.0 5.0 Max Units mV K pF V/s V output referred input referred Conditions
Logic Decoder
Symbol TSU TH VIH VIL lIH lIL Parameter Set-up time-address to enable Hold time-address to enable bar Input logic high voltage Input logic low voltage Input logic high current Input logic low current -1.0 Min 75 75 2.4 0 VDD 1.2 1.0 Typ Max Units ns ns V V A A VIH = VDD VIL = 0 V Conditions
Diode
Symbol PIV VF IF TC Parameter Peak inverse voltage Forward diode drop Forward diode current VF temperature coefficient -2.20 0.60 100 Min Typ Max 5.0 Units V V A
mV/ C
Conditions cathode to anode If = 100A, anode to cathode@25OC anode to cathode anode to cathode
Power Up/Down Sequence
The device can be damaged due to improper power up / down sequence. To prevent damage, please follow the acceptable power up /down sequences and add two external diodes as shown in the diagram below. The first diode is a high voltage diode across VPP and VDD where the anode of the diode is connected to VDD and the cathode of the diode is connected to Vpp. Any low current high voltage diode such as a 1N4004 will be adequate. The second diode is a schottky diode across VNN and DGnd where the anode of the schottky diode is connected to VNN and the cathode is connected to DGnd. Any low current schottky diode such as a 1N5817 will be adequate.
VDD 1N4004 or similar VNN 1N5817 or similar
VPP
Acceptable Power Up Sequences 1) VPP or 1) VNN 2) VNN 2) VDD 3) VDD 3) VPP 4) Inputs & Anode 4) Inputs & Anode
DGND
Acceptable Power Down Sequences 1) Inputs & Anode or 1) Inputs & Anode 2) VDD 2) VPP 3) VNN 3) VDD 4) VPP 4) VNN
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3
HV257
Block Diagram
Byp-VPP Byp-AVDD Byp-AVNN Anode Cathode
VPP AVDD AVNN DVDD DVNN VSIG Bias Circuit
To internal VPP bus To internal analog VDD bus To internal analog VNN bus To internal digital VDD bus To internal digital VNN bus AVDD VPP
CH Q0 Q1 S/H - 0
AVNN
A0 A1 A2 A3 A4 5 to 32 Decoder
R AVDD VPP
CH EN Q31 S/H - 1 DGND
AVNN
R AGND
AVDD VPP
AVNN S/H - 31 To all HVOUT amplifiers R
RSINK
HVOUT Current Sink Limiting
4
-
RSOURCE
CH
-
To all HVOUT amplifiers
+
HVOUT Current Source Limiting
+
+
HVOUT0 AVNN 71R
-
AVNN 71R AVNN 71R
+
+
-
-
DVDD
+
HVOUT1
HVOUT31
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HV257
Truth Table
A4 L L L L * * * H H H X H H H X H H H X A3 L L L L A2 L L L L A1 L L H H * * * L H H X H L H X H H H L A0 L H L H EN H H H H Selected S/H 0 1 2 3 * * * 29 30 31 All Open
Pin Description
VPP BYP-VPP AVDD BYP-AVDD AVNN BYP-AVNN DVDD DVNN DGND AGND A0 to A4 EN Vsig RSOURCE RSINK Anode Cathode HVOUT0 to HVOUT31 High voltage positive supply. There are two pads. A low voltage 1.0 to 10nF decoupling capacitor across VPP and BYP-VPP is required. Analog low voltage positive supply. This should be at the same potential as DVDD. There are two pads. A low voltage 1.0 to 10nF decoupling capacitor across AVDD and BYP-AVDD is required. Analog low voltage negative supply. This should be the same potential as DVNN. There are two pads. A low voltage 1.0 to 10nF decoupling capacitor across AVNN and BYP-AVNN is required. Digital low voltage positive supply. This should be the same potential as AVDD. There are two pads. Digital low voltage negative supply. This should be the same potential as AVNN. There are two pads. Digital ground Analog ground. There are three pads. They need to be externally connected together. Decoder logic inputs. Addressed channel will close the sample and hold switch. Sample and hold switches for unaddressed channels are kept open. Active logic high input. Logic low will keep sample and hold switches open. Common input signal for all 32 sample and hold circuits. External resistor from RSOURCE to VNN sets output current sourcing limit. Current limit is approximately 12.5V divided by Rsource resistor value. External resistor from RSINK to VNN sets output current sinking limit. Current limit is approximately 12.5V divided by RSINK resistor value. Anode side of a low voltage silicon diode that can be used to monitor die temperature. Cathode side of a low voltage silicon diode that can be used to monitor die temperature. Amplifier outpu.ts
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5
HV257
100 1 81 80
100-Lead MQFP (top view)
30 31 50
51
Pin Configuration
DGND
AGND
AGND VSIG
AGND
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HV257
Pad Configuration (not drawn to scale)
Byp-AVDD Byp-AVNN
Do Not Bond. For testing only. Anode Cathode RSINK RSOURCE BYP-VPP VPP HVOUT31 HVOUT30 HVOUT29 HVOUT28 HVOUT27 HVOUT26 HVOUT25 HVOUT24 HVOUT23 HVOUT22 HVOUT21 HVOUT20 HVOUT19 HVOUT18 HVOUT17 HVOUT16 HVOUT15 HVOUT14 HVOUT13 HVOUT12 HVOUT11 HVOUT10 HVOUT9 HVOUT8 HVOUT7 HVOUT6 HVOUT5 HVOUT4 HVOUT3 HVOUT2 HVOUT1 HVOUT0 VPP Do Not Bond. Leave Floating.
AGND
DGND
AVDD
AVNN AVNN AGND
DVNN
DVDD
VSIG
A4 A3 A2 A1 A0 EN
7
AVDD
AGND
DVNN
DVDD
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HV257
Pad Coordinates
Chip size: 17004m x 5480m Center of die is (0,0)
DOC. #: DSFP-HV257
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8
Package Outlines 100 LEAD MQFP PACKAGE OUTLINE (FG)
0.913 (23.2)
70
0.787 (20.0)
51
0.063 (1.6)
71
50
0.551 (14.0) 0.677 (17.2)
100
31
0.063 (1.6)
1 30
0.0256 (0.65)
0.0118 0.0031 (0.30 0.08)
0.0346 0.0059 (0.88 0.15)
0.1063 0.0079 (2.70 0.20) 0.0067 0.0024 (0.17 0.06) 0.0111 0.013 (2.825 0.325)
Note: C ircle (e.g. B ) indicates J E DE C R eference.
Meas urement Legend =
Dimens ions in Inches (Dimens ions in Millimeters )
Doc. #: DSPD-100MQFPFG
A052104
(c)2004 S upertex Inc. All rights res erved. Unauthorized us e or reproduction prohibited.
1235 B ordeaux Drive, S unnyvale, C A 94089 T E L: (408) 222-8888 / F AX : (408) 222-4895 www.s upertex.com

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